1. Field of the Invention
The present invention relates to the testing of integrated circuit (IC) memories, and more particularly, to IC memories having circuitry which, during a test mode of operation, compresses the number of output data bits to fewer than the number of data bits used during the normal mode of operation.
2. Description of the Related Art
As the geometries and cost of integrated circuit memories continues to be reduced, the costs associated with testing the memories is becoming a more significant component of the total manufacturing cost. Specifically, before delivery to end users, each memory chip must be tested to ensure that it is functioning properly.
For example, referring to FIG. 1, a memory chip 20 having 16 data lines DQ[15:0] is connected to a memory chip tester 22 that has at least 16 I/O lines I/O[15:0]. A common testing procedure is to first have the tester 22 send a command to the memory chip 20 to erase all of its bits to "1". The tester 22 then reads the data lines DQ[15:0] in order to verify that they are all "1". Next, zeros are written to all of the bits of the memory chip 20 and the data lines DQ[15:0] are read in order to verify that they are all "0". Then, all of the bits of the memory chip 20 are erased, a checker board pattern "0101010101010101" is written to the memory chip 20, and the data lines DQ[15:0] are read in order to verify that the checker board pattern is present on the data lines. Finally, all of the bits of the memory chip 20 are erased, an inverted checker board pattern "1010101010101010" is written to the memory chip 20, and the data lines DQ[15:0] are read in order to verify that the inverted checker board pattern is present on the data lines. This testing procedure is a good way to find out if any of the bits of the memory chip 20 are shorted to an adjacent bit, to a high level or to a low state, or if there are any other problems.
Memory testers have a limited number of I/O pins, e.g., 32, 64, 128, etc. When memory chips are connected to a tester in the manner shown in FIG. 1, a memory tester having 64 I/O pins can simultaneously test four, 16 bit memory chips. This is because each one of the four memory chips requires 16 of the tester's I/O lines in order for the tester to separately read each of the four memory chips.
Because the cost of testing is becoming such a significant component of the total manufacturing cost of memory chips, it would be desirable to somehow increase the number of memory chips which can be simultaneously tested with a single tester so as to reduce the per chip cost of testing.